|Because of these battery limitations, using a battery to keep the non-volatile memory space is not the best solution. While it has the advantage on not limiting an application by the amount of parameters that can be stored, nvSRAM memories do not depend on stable power being delivered. Once data is stored into a highly-reliable Silicon Oxide Nitride Oxide Silicon (SONOS) EEPROM cell, it will be secure for up to 100 years at 125 degrees Celsius. Designed with proper write-protection schemes, nvSRAM stores data as a charge on an insulator behind an oxide. This means it is immune from noise once the data is stored. This SONOS technology can withstand the highest levels of radiation, which further demonstrates its robustness. A low-power SRAM, on the other hand, is always susceptible to noise and other conducted or radiated emissions.
Studies have also identified weaknesses in dealing with such persistent memory (SSD) architectures where a very large-density and low-power SRAM is kept active replacing the need for a hard disk drive. While this solves the problem of the disk driveís limit of 100 random I/O operations per second, the challenge is how to protect the memory space from program bugs and other brownout and noise related problems.
The reasons that brownouts and spikes can do more damage that a total power loss are subtle. Latent system power should always be fully discharged to create a stable initial system state for proper system power up. Power dips and brownouts can activate an unstable system reset. Voltage drops that just barely reach the reset threshold can, and often do, misfire. This creates poor-quality logic signals that do not always properly configure the systemís power-up logic state.
Complex ASICs, FPGAs, Complex Programmable Logic Devices (CPLDs), and MPUs can power up inconsistently if a proper reset signal is not provided to them. Many of these types of ICs depend upon their own internal reset circuits and do not use the system-wide reset signal. These programmable logic chips are internally configured on power up, and many FPGAs actually read a small EEPROM containing data that programs specific logic function of the chip. Power disruptions can upset this process.
Using a single-reset trip point is usually not an acceptable engineering practice. Reset operations must indicate that the starting logic can function properly and start the configuration process successfully by setting the starting state of all the internal logic on the chip. This works well when power has been off for a lengthy period of time and the system voltage is indeed zero volts.